1. Field of the Invention
The present invention relates to a method for making semiconductor devices and a polishing method, and more particularly to a semiconductor device fabrication method having a process of polishing a high conductivity film, e.g., a copper (Cu) film.
2. Related Art
In recent years, the quest for higher integration and performance in semiconductor integrated circuit (LSI) devices brings development of new microfabrication technologies. Especially, in order to achieve enhanced speed performance of LSI, an attempt is made to change metal wiring material from traditional aluminum (Al) alloys to copper (Cu) or Cu alloys of low electrical resistance (these will be collectively referred to as “Cu” hereinafter). As Cu is difficult in microfabrication by dry etching techniques which have been frequently used in the formation of Al alloy wires, the so-called “damascene” method is mainly employed, which has the steps of depositing a Cu film on a dielectric film with grooves defined therein and then applying thereto chemical-mechanical polishing (CMP) to remove extra portions of the Cu film other than its groove-buried parts to thereby form a pattern of buried wires. A general approach to forming the Cu film is to form a thin seed layer by sputtering and thereafter form by electrolytic plating methods a multilayer film having a thickness of about several hundred of nm. Alternatively, in the case of forming a multilayered Cu wiring pattern, another wire-forming method is usable, which fabricates wires of the type having the so called “dual damascene” structure. In this method, deposit a dielectric film on an underlayer wire. Then, define therein openings, known as via holes, and wiring grooves for the upper-layer wire use, called the trenches. Thereafter, bury a wiring material, such as Cu, to fill both the via holes and the trenches at a time. Next, remove by CMP unnecessary surface portions of the buried Cu for planarization, thereby forming the intended buried wires.
Recently, consideration is given to use as an interlayer dielectric film an insulative material with low dielectric constant, k, which is called the “low-k” film. More specifically, the industry faces challenges for further reduction of the parasitic capacitance between adjacent interconnect wires by replacing traditional silicon dioxide (SiO2) films having a dielectric constant k of about 4.2 by a low-k film with its dielectric constant of 3.5 or less, by way of example.
However, most low-k films have a porous structure in order to achieve low dielectric constants and are thus poor in mechanical strength so that these films can sometimes experience unwanted occurrence of exfoliation or peel-off of a Cu film during CMP process thereof. Such Cu-film peel-off makes it almost impossible to form any intended wires.
The film peel-off and the destruction of a film per se pose serious problems for, in particular, advanced high-performance LSIs of the next generation since these LSIs are designed to use low-k films in order to reduce resistance-capacitance (RC) delays. To avoid such problems, a need is felt to employ a specific polish technique with low friction and increased stability—preferably, without temperature rise-up.
To improve throughputs in microfabrication processes, it is desirable to improve the polishing rate of a Cu film. However, such Cu polish rate increase results in an increase in friction between a polishing pad and the Cu film being polished. This friction increase leads to a further increase of the risk of Cu film peel-off.
Additionally, in order to preclude Cu diffusion into a low-k film, it is a usual approach to form a barrier metal film made of tantalum (Ta) between a Cu film and low-k film. This barrier metal film also is applied CMP planarization by removal of its unnecessary portions. A technique relating to the polishing of such barrier metal film is disclosed, for example, in JP-A-2001-203178. This Japanese patent bulletin teaches a process of polishing a barrier metal film while at the same time dropping down a Cu ionic solution along with a flow of slurry in order to improve the polishing rate of the barrier metal film.